Flat-panel displays such as liquid crystal displays have come into widespread use in recent years. FIG. 20 is a diagram illustrating the general structure of a data driver that outputs level voltages to the data lines of a display section based upon a video signal. As shown in FIG. 20, the data driver includes at least a grayscale voltage generating circuit 920, decoders (selecting circuits) 930 and buffer circuits 910. The grayscale voltage generating circuit 920 comprises a resistor string connected between power supplies VH and VL. Terminals (taps) of the resistor string output grayscale voltages that conform to the number of gray levels. Each decoder 930 receives the grayscale voltages and a digital video signal as inputs, selects a grayscale voltage that corresponds to the video digital signal and outputs the voltage to the respective buffer 910 circuit. The latter current-amplifies the grayscale voltage and outputs the amplified voltage to an output terminal. The output terminals of the buffer circuits 910 are connected to data lines of the display section. A decoder 930 and buffer circuit 910 are provided for every output, and the grayscale voltage generating circuit 920 is shared by all outputs. Further, employed as the video signal supplied to the decoders 930 is a video digital signal that has been processed by a data register, latch and level shifter (none of which are shown), etc.
Since it is required that a data driver perform driving without a variance in the driving grayscale voltage from one of the multiple data lines to the next, the buffer circuits 910 are required to produce an output voltage with high accuracy. Arrangements of the kind shown in FIGS. 21, 22 and 23 have been proposed as being well suited for use in buffer circuits (see Patent Documents 1 and 2, cited below).
FIG. 21 illustrates a differential amplifier circuit that is an offset-canceling amplifier having a function for suppressing output offset caused by element variance of the transistors that construct the circuit. This is disclosed in Patent Document 1, cited below. FIG. 24 is a timing chart illustrating the ON/OFF operation of switches in the circuits of FIGS. 21 to 23.
In terms of operation of the circuit illustrated in FIG. 21, which will be described with reference to the timing chart of FIG. 24, switches SW1 and SW3 are turned ON and switch SW2 is turned OFF in time period t1 of one data output period, as a result of which an input voltage Vin and an output voltage Vout are applied to an input pair of a differential pair (M3, M4) and an input voltage Vin is applied to an input pair of a differential pair (M5, M6). At this time the output voltage Vout is a voltage (Vin+Vf) that includes an offset voltage Vf and is stored in a capacitance element C1.
This is followed by time period t2, at which the switches SW1, SW3 are set in an OFF state and the switch SW2 is turned ON, the input voltage Vin and the voltage (Vin+Vf) that has been stored in the capacitance element C1 are applied to the input pair of a differential pair (M3, M4), respectively, and the input voltage Vin and output voltage Vout are applied to the input pair of a differential pair (M5, M6), respectively.
At this time a voltage identical with that in time period t1 is applied to the differential pair (M3, M4), which operates to hold the differential pair (M5, M6) also in a state identical with that in time period t1. Accordingly, the output voltage Vout in time period t2 becomes a voltage equal to the input voltage Vin and is stable. That is, the circuit arrangement illustrated in FIG. 21 is capable of canceling the output offset and of amplifying and outputting a voltage that is equal to the input voltage.
Further, the arrangement illustrated in FIG. 22 is obtained by modifying the arrangement of FIG. 21 in such a manner that the influence of power supply noise on the output voltage Vout can be suppressed. A capacitor C2, which forms a pair with capacitor C1, is connected to the gate of transistor M3 constituting a differential pair, and a switch SW6 is connected between the gate of transistor M3 and a terminal to which the input voltage Vin is supplied.
In terms of operation of the circuit illustrated in FIG. 22, which will be described with reference to the timing chart of FIG. 24, switches SW1, SW3 and SW6 are set in an ON state and switch SW2 is set in an OFF state in time period t1 of one data output, as a result of which input voltage Vin and output voltage Vout are applied to the input pair of differential pair (M3, M4) and input voltage Vin is applied to the input pair of differential pair (MS, M6). At this time the voltage (Vin+Vf) that includes an offset voltage Vf is stored in the capacitance element C1 and the input voltage Vin is stored in the capacitance element C2.
This is followed by time period t2, at which the switches SW1, SW3 and SW6 are set in an OFF state and the switch SW2 is set in an ON state, the voltages Vin and (Vin+Vf) that have been stored in the capacitance elements C2 and C1 are applied to the input pair of differential pair (M3, M4), respectively, and the input voltage Vin and output voltage Vout are applied to the input pair of differential pair (MS, M6), respectively. In a manner similar to that shown in FIG. 21, the circuit illustrated in FIG. 22 also is capable of canceling the output offset and of amplifying and outputting a voltage that is equal to the input voltage.
It should be noted that in the circuit illustrated in FIG. 22, the voltages that have been stored in the capacitance elements C2 and C1 are applied to the input pair of differential pair (M3, M4) in the time period t2. As a result, even if noise occurs in power supply VSS, the voltages stored in the capacitance elements C2 and C1 fluctuate in the same manner, whereby the effects of noise on the output voltage Vout can be suppressed. Accordingly, the arrangement of FIG. 22 makes possible a voltage output that is more accurate than that obtained with the arrangement of FIG. 21.
Further, the arrangement shown in FIG. 23 also is obtained by modifying the arrangement of FIG. 21. Here the modification is such that a reference voltage Vref is applied to the gate of transistor M3 constituting the input pair.
In terms of operation of the circuit illustrated in FIG. 23, which will be described with reference to the timing chart of FIG. 24, switches SW1, SW3 are set in an ON state and switch SW2 is set in an OFF state in time period t1 of one data output, as a result of which reference voltage Vref and output voltage Vout are applied to the input pair of differential pair (M3, M4), respectively, and input voltage Vin is applied to the input pair of differential pair (M5, M6). At this time the output voltage Vout is a voltage (Vref+Vf) that includes offset voltage Vf with respect to reference voltage Vref. This is stored in capacitance element C1.
This is followed by time period t2, at which the switches SW1, SW3, SW2 are set in an OFF state and the switch SW2 is set in an ON state, the reference voltage Vref and the voltage (Vref+Vf) that has been stored in the capacitance element C1 are applied to the input pair of differential pair (M3, M4), respectively, and the input voltage Vin and output voltage Vout are applied to the input pair of differential pair (M5, M6), respectively.
At this time a voltage identical with that in time period t1 is applied to the input pair of differential pair (M3, M4), which acts to hold the differential pair (M5, M6) also in a state identical with that in time period t1. Accordingly, the output voltage Vout in time period t2 becomes a voltage equal to the input voltage Vin and is stable. That is, the circuit arrangement illustrated in FIG. 23 is capable of canceling the output offset and of amplifying and outputting a voltage that is equal to the input voltage.
In accordance with Patent Document 2, the reference voltage Vref is set to an intermediate voltage in the output voltage range of the amplifying circuit, whereby the amount of fluctuation in the potential of output voltage Vout in time period t1 can be made less than that in the case of FIG. 21. As a result, time period t1, which is the time period in which preparations are made for canceling offset, can be curtailed and time period t2, in which highly accurate drive is performed, can be prolonged.
Patent Document 1:
Japanese Patent Kokai Publication No. JP-P2001-2920041A (FIGS. 1 and 8)
Patent Document 2:
Japanese Patent Kokai Publication No. JP-P2003-168936 (FIG. 1)